The present disclosure relates to a solid-state image pickup device represented by a complimentary metal-oxide-semiconductor (CMOS) image sensor and a camera system.
An output circuit of a charge-coupled device (CCD) as a solid-state image pickup device (image sensor) is typically a one-channel (ch) output for which a floating diffusion (FD) amplifier including an FD layer is used.
On the other hand, a CMOS image sensor includes an FD amplifier for each pixel therein, and the output thereof is typically of a column-parallel output type, in which a certain row is selected in a pixel array and read in a column direction at the same time.
This is because it is difficult to obtain a sufficient driving capability with the FD amplifier provided within a pixel and therefore the data rate is to be decreased, which can be advantageously realized by parallel processing.
Such a CMOS image sensor is widely used in an image pickup apparatus such as a digital camera, a camcorder, a monitoring camera, or an on-vehicle camera as an image pickup device.
FIG. 1 is a diagram illustrating an example of the general configuration of a CMOS image sensor in which pixels are arranged in a two-dimensional array.
A CMOS image sensor 10 illustrated in FIG. 1 includes a pixel array unit 11, a row selection circuit 12, and a read circuit (column processing circuit: AFE) 13.
In the pixel array unit 11, pixel circuits are arranged in a matrix having M rows and N columns.
Power supply voltage VDD is directly supplied to the pixel array unit 11.
The row selection circuit 12 controls the operation of pixels arranged in an arbitrary row in the pixel array unit 11. The row selection circuit 12 controls the pixels through control lines LSEL, LRST, and LTRG.
The read circuit 13 receives data regarding the row of pixels subjected to the read control by the row selection circuit 12 through a signal output line LSGN, and transfers the data to a signal processing circuit in a later stage.
The read circuit 13 includes a correlated double sampling (CDS) circuit and an analog-to-digital converter (ADC).
FIG. 2 is a diagram illustrating an example of the pixel circuit in the CMOS image sensor including four transistors.
A pixel circuit 20 includes, for example, a photoelectric conversion element (hereinafter also referred to simply as a PD) 21 including a photodiode (PD). The pixel circuit 20 includes, for this single photoelectric conversion element 21, four transistors, namely a transfer transistor 22, a reset transistor 23, an amplifier transistor 24, and a selection transistor 25, as active elements.
The photoelectric conversion element 21 converts incident light into a certain amount of electric charge (here, electrons) in accordance with the amount of the incident light.
The transfer transistor 22 is connected between the photoelectric conversion element 21 and a floating diffusion FD (hereinafter also referred to simply as an FD), and a transfer signal (driving signal) TRG is supplied to the gate (transfer gate) of the transfer transistor 22 through the transfer control line LTRG.
Thus, the electrons that have been subjected to the photoelectric conversion by the photoelectric conversion element 21 are transferred to the floating diffusion FD.
The reset transistor 23 is connected between a power supply line LVDD and the floating diffusion FD, and a reset signal RST is supplied to the gate of the reset transistor 23 through the reset control line LRST.
Thus, the potential of the floating diffusion FD is reset to the potential of the power supply line LVDD.
The gate of the amplifier transistor 24 is connected to the floating diffusion FD. The amplifier transistor 24 is connected to a signal line 26 (LSGN illustrated in FIG. 1) through the selection transistor 25 to configure a constant-current source and a source follower outside the pixel.
An address signal (selection signal) SEL is supplied to the gate of the selection transistor 25 through the selection control line LSEL, and the selection transistor 25 is turned on.
When the selection transistor 25 has been turned on, the amplifier transistor 24 amplifies the potential of the floating diffusion FD and outputs voltage according to the potential to the signal line 26. The voltage output from each pixel through the signal line 26 is output to the read circuit.
In a reset operation of each pixel, electric charge accumulated in the photoelectric conversion element 21 is transferred to the floating diffusion FD and then discharged by turning on the transfer transistor 22.
At this time, the reset transistor 23 is turned on in advance and discharges the electric charge to the power supply side, so that the floating diffusion FD can receive the electric charge in the photoelectric conversion element 21. Alternatively, the reset transistor 23 is turned on while the transfer transistor 22 is turned on, in order to directly discharge the electric charge to a power supply.
This series of operations will be referred to simply as the “pixel reset operation” or the “shutter operation”.
On the other hand, in a read operation, first, the reset transistor 23 is turned on to reset the floating diffusion FD, and the selection transistor 25 is turned on in this state to output the electric charge to the output signal line 26. This is called “P-phase output”.
Next, the transfer transistor 22 is turned on to transfer the electric charge accumulated in the photoelectric conversion element 21 to the floating diffusion FD, and the output of the floating diffusion FD is output to the output signal line 26. This is called “D-phase output”.
A difference between the D-phase output and the P-phase output is obtained outside the pixel circuit, and reset noise of the floating diffusion FD is cancelled to obtain an image signal.
This series of operations will be referred to simply as the “pixel read operation”.
The transfer control line LTRG, the reset control line LRST, and the selection control line LSEL are selectively driven by the row selection circuit 12.
As the configuration of the pixel circuit, a three-transistor configuration (3Tr type) pixel circuit, a five-transistor configuration (5Tr type) pixel circuit, and the like may be adopted instead of the four-transistor configuration (4Tr type) pixel circuit.
The 3Tr-type pixel circuit does not include a transfer transistor that controls the movement of electric charge from the photoelectric conversion element (PD) 21 to the floating diffusion FD in accordance with the potential of the transfer control line LTRG.
FIG. 3 is a diagram illustrating another example of the pixel circuit in the CMOS image sensor including four transistors.
In a pixel circuit 20A illustrated in FIG. 3, the reset transistor is connected to a power supply line LVREF different from the power supply line LVDD.
That is, in the pixel circuit 20A, the reset transistor 23 is connected between the power supply line LVREF and the floating diffusion FD, and the reset signal RST is supplied to the gate of the reset transistor 23 through the reset control line LRST.
Thus, the potential of the floating diffusion FD is reset to the potential of the power supply line LVREF.
In Japanese Unexamined Patent Application Publication No. 2008-283501, a technique for driving a pixel circuit including supply of power supply voltage is described.